The present invention relates to a semiconductor device, and particularly to a technique effective if applied to a semiconductor device including a nonvolatile semiconductor memory device.
As one of electrically programmable/erasable nonvolatile semiconductor memory devices, an EEPROM (Electrically Erasable and Programmable Read Only Memory) has been widely used. Each of these memories typified by a flash memory widely used at present has a conductive floating gate electrode and a trap insulating film surrounded by an oxide film, which are placed below a gate electrode of a MISFET, sets a charge stored state at the floating gate or trap insulating film as memory information, and reads it as the threshold voltage of the transistor. The trap insulating film corresponds to an insulating film capable of storing an electrical charge.
As one example, may be mentioned a silicon nitride film or the like. The threshold voltage of the MISFET is shifted by injection/discharge of the electrical charge into and from such a charge storage region and the trap insulating film is operated as a memory element. As the flash memory, may be mentioned a split gate type cell using a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) film. Such a memory has the advantages that the use of the silicon nitride film as the charge storage region brings about excellent reliability of data retention because the electrical charge is stored on a discrete basis, as compared with a conductive floating gate film, and the oxide films provided above and below the silicon nitride film can be thinned because the reliability of the data retention is excellent, whereby reductions in the voltages for write/erase operations are made possible.
A technique related to the layout of contacts relative to gate electrodes of a nonvolatile semiconductor memory device has been described in Japanese Unexamined Patent Publication No. 2003-100915 (corresponding to USP 2003/0057505A1) (refer to a patent document 1).
A technique for applying different voltages to word lines of memory cells opposed with a bit line interposed therebetween upon a write operation has been described in Japanese Unexamined Patent Publication No. Hei 6 (1994)-333397 (refer to a patent document 2).